Intel launches Hybrid Bonding technology to promote the evolution of high-end packaging

Recently, Intel shared the Intel packaging technology roadmap with the outside world. Johanna Swan, an Intel academician and director of packaging research and system solutions, shared that from standard packaging to an embedded bridge, the bump pitch has changed from 100 microns to 55-36 microns. When it comes to Foveros packaging, Intel stacks the chips together to achieve horizontal and vertical interconnections, with a bump pitch of about 50 microns. In the future, Intel will adopt Hybrid Bonding (there are two translations: hybrid bonding, hybrid bonding) technology to plan to achieve a bump pitch of fewer than 10 microns.

How does Hybrid Bonding technology achieve the reduction of the bump pitch to less than 10 microns?

Hybrid Bonding technology subverts welding technology

Intel published a paper on hybrid bonding technology at ECTC this year. Johanna Swan introduced that hybrid bonding technology is a way to obtain denser interconnections between stacked chips and help achieve smaller form factors.

When reduced to a bump pitch of about 10 microns, it will be able to reach 10,000 bumps per square millimeter. In this way, more interconnections can be achieved between the two chips, and a smaller and simpler circuit can be provided because they can be superimposed on each other without fan-in and fan-out.

"With this simpler circuit, we can use a lower capacitance, and then start to reduce the power of the channel, which helps to develop in the direction of providing the best product." Johanna Swan said.

There are many differences between Hybrid Bonding and Foveros technology.

Hybrid bonding technology makes the dielectric chip very smooth instead of having a prominent bump. In fact, there will be a slight depression. When the two components are put together using hybrid bonding technology, it can be done at room temperature. After they are placed, the temperature is raised to anneal them, and the copper will expand at this time to form an electrical connection.

Johanna Swan believes: "This is very useful because it can achieve higher current carrying capacity and can reduce the pitch to less than 10 microns. This allows us to obtain better than underfill and tight copper density between these interfaces. Thermal performance. When hybrid bonding technology is used, a new method of manufacturing, cleaning, and testing will be required."

It may be more attractive to switch to a smaller pitch. Intel is shifting to multiple chips, decomposing them into GPUs, CPUs, IOs, or blocks. Later, they may be able to use smaller blocks to have separate IPs, which makes it possible to have more blocks and reuse them. Johanna Swan pointed out that this technology can customize products according to the unique needs of specific customers. This technology can change the wafer-to-die interconnect, from soldering to hybrid bonding.

If the manufacturing process must be kept at the same speed, what should be done when more wafers need to be placed? To this end, the solution Intel is considering is mass assembly, referred to as "self-assembly."

Currently, Intel is cooperating with CEA-LETI (French Atomic Energy Commission Electronics and Information Technology Laboratory) to study the ability to place multiple chips at a time and perform self-assembly.

Packages will continue to be miniaturized and reduced in size

On the scalability axis, it includes CO-EMIB technology and ODI all-around interconnection technology.

CO-EMIB technology attempts to use a combination of EMIB and Foveros to fuse 2D and 3D technologies. This architecture is based on high-density connections with matching chips and stacked chip composites, achieving a size larger than the basic size.

ODI, a full range of interconnection technology, is a new dimension of packaging that Intel is using.

For the combination of 2.5D and 3D, Johanna Swan pointed out that this trend will definitely continue because the development opportunity is to provide as many blocks per millimeter cube and get as many functions as possible per millimeter cube. The package will continue to be miniaturized and reduced in size so that the maximum functionality of the millimeter cube can be obtained.

Intel's Foveros technology, through which the chips are stacked, uses Through-Silicon-Via (TSV) technology to communicate between the package and the wafer, all the way to the top wafer.

However, ODI packaging technology is another optimization, customized for customers by adding ODI packaging technology. Pillars have been added to the right to allow the top die on the far right to be directly connected to the package, which allows a smaller TSV chip area to be used through-silicon vias (TSV), thereby reducing the number. These pillars provide the ability to directly supply power to the top chip package. The two crystals on the top have higher bandwidth, smaller bumps, and smaller channels for the lower wafer.

Regarding how to promote the continuous evolution of packaging, Johanna Swan believes: “Packaging is a differentiating factor, and the key is customers. We strive to serve and provide unique solutions to customers, which also promotes our attention to technology. Therefore, packaging The opportunity is that as customers continue to provide services to customers, customer product needs continue to evolve. This is the reason that really promotes the need to transform packaging technology. This differentiated demand of customers will also promote the emergence of corresponding packaging technology.

In order to meet the needs of customers, wafer manufacturing companies have begun to devote themselves to advanced packaging technology, which has also blurred the boundaries between wafer manufacturing and packaging. Regarding the future development trend of the two, Johanna Swan also expressed her own understanding: "In the hybrid bonding of 10-micron pitch, the two worlds have begun to merge. I began to study the characteristics of the metal layer we are using below 10 microns, like 4 microns. Wafer manufacturing and packaging are merging, which has become a very important and interesting place for innovation because they are the same size, so this placement is very exciting, using the traditional packaging and testing technology Fab tools have created a whole new area for us to innovate in packaging.