Samsung announced the successful tapeout of 3nm!

Samsung is one step closer to TSMC! According to the latest reports from foreign media, Samsung announced that its 3nm process technology has been officially tapped out.

Reports show that Samsung's 3nm process uses GAA architecture, which is better than the FinFET architecture used by TSMC 3nm from a performance perspective. However, due to the GAA architecture rather than the FinFET architecture, Samsung needed a new design and certification tools, and thus adopted Synopsys’ Fusion Design Platform, with the aim of accelerating the provision of a highly optimized reference method for the production process of the GAA architecture.

According to Samsung, the logic area efficiency of 3nm GAA technology is increased by more than 35%, power consumption is reduced by 50%, and performance is improved by about 30% compared with the 5nm manufacturing process. Sangyun Kim, vice president of Samsung's foundry design technology team, said: "Samsung Foundry is the core to promote the next stage of industry innovation. We continue to develop based on process technology to meet the growing needs of professional and wide-ranging market applications. Our latest The advanced 3nm GAA process benefited from our extensive cooperation with Synopsys, and the accelerated preparation of Fusion Design Platform to effectively realize the promise of the 3nm process proved the importance and benefits of these key alliances."

Of course, what has attracted widespread attention in the industry is not only the performance improvement brought by the 3nm process but also Samsung's bold attempt on the GAA architecture. Why did Samsung adopt the GAA architecture instead of following TSMC’s FinFET path?

As we all know, every step of the semiconductor process after entering the node below 32nm is full of hardships. Scientists and engineers have also invented various enhancement technologies in the past few years to counter the uncertainty caused by continued scaling. But the quantum effect is always a stumbling block on the road to advanced manufacturing. Now that we have entered the era of 7nm and 5nm, there will be new troubles if we want to move forward to smaller process nodes.

The mainstream technology of existing semiconductor manufacturing is mostly carried out by "fin transistor" or FinFET technology, which has successfully continued the development of several generations of semiconductor technology below 22nm. From the perspective of technological development, after the planar transistor size is reduced to 22nm, the leakage current control will become very difficult. This is because the "barrier tunneling effect" causes current leakage.

The so-called "barrier tunneling effect" means that although the source and drain are separated by an insulating object and cannot be turned on after the insulating layer becomes thinner and thinner, the distance between the source and the drain is getting closer and closer. In the end, the two are too close, and a slight application of voltage will cause the electrons to penetrate the insulating layer to the other end in a probabilistic manner, which brings about leakage current and power consumption problems. The solution to the problem is FinFET, that is, the drain and source are "stand up", and the gate is constructed vertically to form a classic FinFET "fin" structure. This classic structure not only thickens the insulating layer to a large extent and solves the tunneling effect of planar transistors, but also brings more effective contact surfaces to the gate, which reduces current resistance and heat generation.

Since the 22nm era, FinFET has become a magic weapon for various manufacturers to reduce the size of transistors. But no matter how good the magic weapon is, it will fail one day. As the size of transistors moves towards 5nm or even 3nm, the size of FinFET itself has shrunk to the limit. Whether it is fin distance, short channel effect, leakage, and material limitations, transistor manufacturing has become precarious, and even the physical structure cannot be completed.

A typical example is that after 5nm, FinFET has almost reached its physical limit, and the ratio of its continuously increased depth to width (in order to avoid short-channel effects, the width of the fin should be less than 0.7 times the gate length ), will make it difficult for the fin to maintain an upright shape under the internal stress of its own material, especially after the introduction of a higher energy EUV process, this situation will be more serious, and even photons will appear quantum at such a small scale The effect thus brings a lot of exposure noise, which seriously affects the quality and performance of the product. In addition, the grid distance is too small will bring an uncontrollable situation.

Take the Intel process as an example. In the 14nm process, the gate pitch is 70nm, and in the 10nm process, the gate pitch is 54nm. The gate pitch is shrinking as the process evolves. IMEC’s simulations show that the limit of the gate pitch under the existing FinFET technology is 42nm. When the process reaches 5nm or even 3nm, the gate pitch will shrink. When it is less than 42nm, people The proud FinFET will not continue to be used.